Package: openocd-0.11.0 Version: 0.11.0-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 5738 Depends: libc6 (>= 2.38), libcapstone4 (>= 4), libftdi1-2 (>= 1.5), libgpiod2t64 (>= 1.1), libhidapi-hidraw0 (>= 0.8.0~rc1+git20140201.3a66d4e+dfsg), libjim0.82t64 (>= 0.73), libusb-0.1-4 (>= 2:0.1.12), libusb-1.0-0 (>= 2:1.0.16) Filename: amd64/openocd-0.11.0_0.11.0-1_amd64.deb Size: 2014884 MD5sum: fac63b5b04ae8a606b5fb2bb9c3b3fe3 SHA1: ba966234a37a628b984d6af1f6dec835fbbaf9b9 SHA256: 0406002797b1d5f61a592585afcebc403f4acfc3e8f37a6ce118595d389d9190 Section: embedded Priority: optional Homepage: http://openocd.sourceforge.net/ Description: Open on-chip JTAG/SWD debug solution for embedded target devices OpenOCD aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices. . The debugger uses an IEEE 1149-1 compliant JTAG TAP bus master to access on-chip debug functionality available on ARM based microcontrollers or system-on-chip solutions. For MIPS systems the EJTAG interface is supported. Additionally there is support for eSi-RISC, Intel, OpenRISC, RISC-V and ARC controllers. . User interaction is realized through a telnet command line interface, a gdb (the GNU debugger) remote protocol server, and a simplified RPC connection that can be used to interface with OpenOCD's Jim Tcl engine. . OpenOCD supports many different types of JTAG interfaces/programmers. Package: openocd-0.11.0-dbgsym Source: openocd-0.11.0 Version: 0.11.0-1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 5032 Depends: openocd-0.11.0 (= 0.11.0-1) Filename: amd64/openocd-0.11.0-dbgsym_0.11.0-1_amd64.deb Size: 4755072 MD5sum: 9119f5eab235e09bce80df961ff612fc SHA1: ba75fb8da1db52adafbc027e8ea30c2e80608e8c SHA256: 521b0a2543ed82e399e953ed0d2483e031dd9e5b6b89420044cd771a4bef2aa3 Section: debug Priority: optional Description: debug symbols for openocd-0.11.0 Build-Ids: a2c8f2d20d3804bd24b522a569b84b5af6753790 Package: verilator-4.032 Version: 4.032-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 19878 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.032_4.032-1_amd64.deb Size: 4541648 MD5sum: 718f136f41d295cd6ad939ac5bf02e21 SHA1: 39395c53ec1d7036e13f297f77eedd6bf3197b88 SHA256: 6e1cfb6c7d1312bf0467830b6c012e8d7965ca8ee71fb919a41ae20c7a966495 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.032-dbgsym Source: verilator-4.032 Version: 4.032-1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 93779 Depends: verilator-4.032 (= 4.032-1) Filename: amd64/verilator-4.032-dbgsym_4.032-1_amd64.deb Size: 89227720 MD5sum: 63316e852d37470420a18827434c6dd9 SHA1: 6bfb58fc43e27515a3a88224e8a26b423c0867f9 SHA256: 27bbc668aef46c317e82cf71fde17d2e53a74f936534dd20414db74ed4be09b0 Section: debug Priority: optional Description: debug symbols for verilator-4.032 Build-Ids: 06d23bb4dc1419d6af8bebdc2aa83fa11deb3fb9 21ce6f91fa5ed737df33773ef62769cbc2cba545 2202d25d8f80ec6e1ee52959cfcf9d486b7429a1 Package: verilator-4.034 Version: 4.034-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20397 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.034_4.034-1_amd64.deb Size: 4634424 MD5sum: 892cde7bb85de3706c8b439cf64cadb3 SHA1: 1a28d1160870b866d3e3bac1d1328c3db35d0ddc SHA256: 3c7508c6bbe9748f49d3dce85ca752710a2df0da9084f1edf290a624178b2e91 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.034-dbgsym Source: verilator-4.034 Version: 4.034-1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 96244 Depends: verilator-4.034 (= 4.034-1) Filename: amd64/verilator-4.034-dbgsym_4.034-1_amd64.deb Size: 91645244 MD5sum: d739e45beda6adee6a5a88998cb87d2b SHA1: cf96ac89225151b109cf8dfe2a2939fdf67871bb SHA256: 713f87fa5aa335e03abd3ea7229be1f1f72feda8cd8c01d2580b2ddb89165fc1 Section: debug Priority: optional Description: debug symbols for verilator-4.034 Build-Ids: 16df12c1ecc4b1091405f4213b60051a4a5c3f89 cbf94207623bb32db724c6b9db10fe8d82c2fa7c dc87f114a6535b5b4f9a17b568195a42b271fad8 Package: verilator-4.040 Version: 4.040-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 21428 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.040_4.040-0_amd64.deb Size: 4920532 MD5sum: 0fa581c463340b090f6dac2a2eec8408 SHA1: 8660b25a5df4556f03f54cf8eff40f6a8a11149a SHA256: 0fad5848e788d026ef8c6856a4fcade916fa4796890cf48d6b538928c8daea22 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.040-dbgsym Source: verilator-4.040 Version: 4.040-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 103108 Depends: verilator-4.040 (= 4.040-0) Filename: amd64/verilator-4.040-dbgsym_4.040-0_amd64.deb Size: 98478192 MD5sum: 8d7f1de28f40b16d0ee10a08bad5cb27 SHA1: fa2d27f650eeb7ecdfb58339af71cdf6b19331de SHA256: 1cee19994e0d0c2900ac56cbbe23b260dbb36e539ebd59f31ff97da04519da09 Section: debug Priority: optional Description: debug symbols for verilator-4.040 Build-Ids: 5241ab5ffa4d756c11c108aed7721f86e6be2669 79cae976c64f2a04b0e86be2bf9ae4526352accf bf179656b8a4c8fbab6a99b2de5ca07ee3c8238b Package: verilator-4.100 Version: 4.100-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 21810 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.100_4.100-0_amd64.deb Size: 5038140 MD5sum: bb2518de778a6fbeed87c9000438e90b SHA1: fad7e76bd32ac571f6d140c93f3f763c51b72117 SHA256: 1e535d2cc82494325a2314366f7fa871bcbb60c99a4d80b652793dab08c4f1e6 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.100-dbgsym Source: verilator-4.100 Version: 4.100-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 107873 Depends: verilator-4.100 (= 4.100-0) Filename: amd64/verilator-4.100-dbgsym_4.100-0_amd64.deb Size: 103219380 MD5sum: 7b4f324952c1e588c255ddf964088677 SHA1: 69995d87f9f25491f559e5d3e75f28314b4185a6 SHA256: 2824882484b85390fd75b68027a9a1dffd2226bbef927aac50e607cc511d7922 Section: debug Priority: optional Description: debug symbols for verilator-4.100 Build-Ids: 81925b7c6b8f7d80c5779ea48ea206072af1e779 c03a0230820c354e3d688b067e3f8282d943f2f8 d614f64ac487d01404aab44aee53adae134628a9 Package: verilator-4.102 Version: 4.102-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 21784 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.102_4.102-0_amd64.deb Size: 5019964 MD5sum: c6ba46474ede49e91bf6781c5af59031 SHA1: 778bdc4b1c5f78cb692fb4524969dadd9b50c253 SHA256: e786d2108d556d17214fd9c87269c2620b0ce9205ffc2e640c1168dc80c4f97d Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.102-dbgsym Source: verilator-4.102 Version: 4.102-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 107373 Depends: verilator-4.102 (= 4.102-0) Filename: amd64/verilator-4.102-dbgsym_4.102-0_amd64.deb Size: 102718952 MD5sum: a0b5ac53cc9a154caa66a08ffce15834 SHA1: 966a65a28d23ef2e5272c615e05f39b5daeb734e SHA256: 313d11f065fcb253d52039f0eb21b012201b96e418b6bbcb003bc1f159dc0b19 Section: debug Priority: optional Description: debug symbols for verilator-4.102 Build-Ids: 36487c6acb2a781df56cfefaa9db9ac6cb4299ae 6c90f7f32589747f9c56b1d68a760bc4cd9f52db eafd3ea5c9eb9f4ca66750f53f2a731f6d9fd141 Package: verilator-4.104 Version: 4.104-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20322 Depends: libc6 (>= 2.29), perl, perl-doc Filename: amd64/verilator-4.104_4.104-0_amd64.deb Size: 4408228 MD5sum: 779eafdf157ac8bb70bbefcd735b888c SHA1: ea833cdbe03794a817433175695c93c1a7b6da07 SHA256: 9f3f9106d161923cb58b726aeffba98d391aeb8aefa5b2ab0d2232283e918638 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.104-dbgsym Source: verilator-4.104 Version: 4.104-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 102330 Depends: verilator-4.104 (= 4.104-0) Filename: amd64/verilator-4.104-dbgsym_4.104-0_amd64.deb Size: 100306748 MD5sum: 2b3ea6cd2ea3deecf8f894680172ac94 SHA1: 1335f006f8e3e7aac9030a78e7ef3ff9217ed2bd SHA256: f6714bae72bb1ea92e8915af9dffc758e983d69c39a3e578ea47315ba4d394c2 Section: debug Priority: optional Description: debug symbols for verilator-4.104 Build-Ids: 61cdf0b255dcc955bc44e0c4912d15fdcf11e84a 86703e7c786ab3e965062070ee26e7013bff5677 8cbf0e56cab49d7e5433279e9fd6efda50a90609 Package: verilator-4.106 Version: 4.106-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20416 Depends: libc6 (>= 2.29), perl, perl-doc Filename: amd64/verilator-4.106_4.106-0_amd64.deb Size: 4417856 MD5sum: 88b0494d3cb18532849bc6cdf655a111 SHA1: 7076825318d694aa7dda86ee3eb22c43fc7d087d SHA256: 32e32a724d6e900052791f97a98f1d815ffbdee0d8b11fbc05f35a0d4b29f782 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.106-dbgsym Source: verilator-4.106 Version: 4.106-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 103068 Depends: verilator-4.106 (= 4.106-0) Filename: amd64/verilator-4.106-dbgsym_4.106-0_amd64.deb Size: 101008296 MD5sum: d36f762bd5921596fc126b8411c2d7b5 SHA1: 58817e79686033d2282693c952baaef41e096f0d SHA256: 0e67f26b9e782d94d06850f56df73f975cd849a5ff0e684708ee1d15b2342379 Section: debug Priority: optional Description: debug symbols for verilator-4.106 Build-Ids: 16820fd8c7031453450c6e4e6481c61858d586e4 1d3461a93e7edb98bb4aaa70d243c21f19c29032 cb2c2b8209447c85ce0d240b735166dfa3782138 Package: verilator-4.108 Version: 4.108-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20630 Depends: libc6 (>= 2.29), perl, perl-doc Filename: amd64/verilator-4.108_4.108-0_amd64.deb Size: 4523440 MD5sum: 91f5dec8111bf721bae9172b80535ca6 SHA1: 4173b8133519a5b3079123e1f07ae6cddb43bd79 SHA256: cf1dfead6a1929e0fc41e6628ab6288a409ac86957532ed63647be01a069cf8c Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.108-dbgsym Source: verilator-4.108 Version: 4.108-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 104444 Depends: verilator-4.108 (= 4.108-0) Filename: amd64/verilator-4.108-dbgsym_4.108-0_amd64.deb Size: 102356652 MD5sum: 69c4e8f25d0d295ddabe0c5064702791 SHA1: 54e532c0b7839e39e6b83c041aaebcce66a9fb09 SHA256: 4a348a344922f7c2a41eb02f587decf43d0a347b38a3e98dc2fdf725a7a0ce3a Section: debug Priority: optional Description: debug symbols for verilator-4.108 Build-Ids: 0a71845dbeffd451e4267e68e5b6e94001cdd40a aa08307d793992d30ebb2c6021f7a301b2182f12 b96a9c3a9e5a76e4438b5a8d74b5b161d508c82a Package: verilator-4.110 Version: 4.110-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22438 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.110_4.110-0_amd64.deb Size: 5157512 MD5sum: ca46c80e47c95ed6f0a70ceedd1d49f1 SHA1: 76f2cbef0f074571035e54850834bd34515a2c6e SHA256: 306142ad3c363055eaf949a501996cda9e76dd4ddc1096a993c9b2992aa1d5f8 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.110-dbgsym Source: verilator-4.110 Version: 4.110-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 110887 Depends: verilator-4.110 (= 4.110-0) Filename: amd64/verilator-4.110-dbgsym_4.110-0_amd64.deb Size: 106113796 MD5sum: 4cb81efa2227a7fd3af60e601023e69a SHA1: 1c62022ea07865f19f826fd4c4ffa4932b03b7eb SHA256: 28eea44e6c65eefcb19ca28cf4a98c8ab4ae05a2135a61800cc4684f979727a5 Section: debug Priority: optional Description: debug symbols for verilator-4.110 Build-Ids: 73b90ebca27bceb48de4a6c4ddc59bb5f994b8d3 7d5476018a5658f22984831be7b5d7c5bd492128 d4721115305b6eb08976bd4c0260b5192b190c2e Package: verilator-4.200 Version: 4.200-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22476 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.200_4.200-0_amd64.deb Size: 5169876 MD5sum: ef700f2a0eb5bde48316bbfe49d104c8 SHA1: f545581975336d34c44ad8fd7ba49796d77f307b SHA256: 96431ed4a15c712b93b6f7d91b5e76f2dee910532142cea4c09886861c5a2f83 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.200-dbgsym Source: verilator-4.200 Version: 4.200-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 110664 Depends: verilator-4.200 (= 4.200-0) Filename: amd64/verilator-4.200-dbgsym_4.200-0_amd64.deb Size: 105903084 MD5sum: 5d6aedcd408e4b31900bbe1d22bf6e53 SHA1: 007fa42ec5b2907a24f91dc5f332db5faf80a3f6 SHA256: ede39bb44eac2fabefc0f921a26d68b27e4fb7202f30101144fc55b15541d307 Section: debug Priority: optional Description: debug symbols for verilator-4.200 Build-Ids: 64a578edc44829fdc07eca917d6415d5c45f9744 854f373cab81662d13875f6fc4009c593c48d763 f6dba2aaae9437bf3071fa97d2dab7e392016640 Package: verilator-4.202 Version: 4.202-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20844 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.202_4.202-0_amd64.deb Size: 4505760 MD5sum: 44b9a94630e04e15c6230ff477b9aefa SHA1: 4039852037ba40ffc0108ba362c510e6a56bd1d8 SHA256: 87399722ea9e0e53d1ca0b1b9e13389684c8921e857a1c1029d52d536f7452a0 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.202-dbgsym Source: verilator-4.202 Version: 4.202-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 104300 Depends: verilator-4.202 (= 4.202-0) Filename: amd64/verilator-4.202-dbgsym_4.202-0_amd64.deb Size: 103003528 MD5sum: 843cb2183b6b4eb552f6a440603d61c7 SHA1: 094017a80e113c54da01227ffaccdb54e003f92f SHA256: d850226867855c07d7c043fa5dccd42ffe23b3ba67bb2fa22388f03404476279 Section: debug Priority: optional Description: debug symbols for verilator-4.202 Build-Ids: 072308c5c3229203257ffb950d691430b70cfb8e 2363be2e94a73270f77a9cf1d9e5fee7711079cb f1075dc171c5d60699d47762b225c03edc6d7d00 Package: verilator-4.210 Version: 4.210-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22649 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.210_4.210-0_amd64.deb Size: 4628644 MD5sum: dac49879c3740f3418bc6b2c73c5df87 SHA1: 43e6490d1d751cc815c191b25d9b6f9fabf25424 SHA256: 3528a25c7448cd0587f3e500774010ca839cf14decd8cae7670d4294eb6593c2 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.210-dbgsym Source: verilator-4.210 Version: 4.210-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 111162 Depends: verilator-4.210 (= 4.210-0) Filename: amd64/verilator-4.210-dbgsym_4.210-0_amd64.deb Size: 109152212 MD5sum: b006614cb22c27d9971b1de27461d184 SHA1: 11c8790495fc6afd7dcdabf164f1d9a58952ea9e SHA256: 41d7a25ca42bd17c15f9b14b0463af5bfcd5c5352aaa0cac7e9d01199695bb57 Section: debug Priority: optional Description: debug symbols for verilator-4.210 Build-Ids: 4962b49bc23d30c07c1aef479e0a849bb6e2eeb0 7f017f23b6b1ff7bd47d47b895808b532149a8ab ef42827638c8358488735750d141f2b4da1658aa Package: verilator-4.212 Version: 4.212-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22922 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.212_4.212-0_amd64.deb Size: 4686672 MD5sum: 33f3962069e72a6bc807d52ac2e053b1 SHA1: bca1329e852185068ff7e5cc3ceb7a27efae2bc1 SHA256: 1daed6d0f821ad30464c5b10f478c56eaad122ecee29c9e6d4ea359e31b9b2da Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.212-dbgsym Source: verilator-4.212 Version: 4.212-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 114409 Depends: verilator-4.212 (= 4.212-0) Filename: amd64/verilator-4.212-dbgsym_4.212-0_amd64.deb Size: 112406048 MD5sum: bef88835df351c5aa415f8274d5b4381 SHA1: b2397af0ee6bfe7d3493555f5e26e2050b7e12dc SHA256: a91e2cc1dbff89138c22822234524ade622eae84d90ff1a5ecd04602a651f061 Section: debug Priority: optional Description: debug symbols for verilator-4.212 Build-Ids: 6c9af321c93026af834c971331c60f526c774076 b1e69798d75108d40e98583ce22ba9f68256141b e61aa1195ae742ba6823d408ac971a007e204828